1. Formal Semantics and Proof Techniques for Optimizing VHDL Models
Author: by Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey.
Library: Center and Library of Islamic Studies in European Languages (Qom)
Subject: Computer engineering.,Computer hardware.,Computer-aided design.,Engineering.,Systems engineering.
2. Formal semantics and proof techniques for optimizing VHDL models
Author: Umamageswaran, Kothanda
Library: Central Library of Sharif University of Technology (Tehran)
Subject: ، VHDL )Computer hardware description language(
Classification :
TK
7885
.
7
.
U43
1999
